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There are several families of logic ICs numbered from 74xx00 onwards with letters xx in the middle of the number to indicate the type of circuitry, eg 74LS00 and 74HC The original family now obsolete had no letters, eg For each IC there is a diagram showing the pin arrangement and brief notes explain the function of the pins where necessary.
For simplicity the family letters after the 74 are omitted in the diagrams below because the pin connections apply to all ICs with the same number. If you are using another reference please be aware that there is some variation in the terms used to describe pin functions, for example reset is also called clear. Some inputs are 'active low' which means they perform their function when low. Note that 74HC inputs cannot be reliably driven by 74LS outputs because the voltage ranges used for logic 0 are not quite compatible, use 74HCT instead.
The minor disadvantage of 74HCT is a lower immunity to noise, but this is unlikely to be a problem in most situations. For most new projects the 74HC family is the best choice. Some 74 series ICs have open collector outputs, this means they can sink current but they cannot source current.
The diagram shows how an open collector output can be connected to sink current from a supply which has a higher voltage than the logic IC supply. The maximum load supply is 15V for most open collector ICs. Touching a pin while charged with static electricity from your clothes for example may damage the IC. In fact most ICs in regular use are quite tolerant and earthing your hands by touching a metal water pipe or window frame before handling them will be adequate.
ICs should be left in their protective packaging until you are ready to use them. It is best to build a circuit using just one logic family, but if necessary the different families may be mixed providing the power supply is suitable for all of them. For example mixing and 74HC requires the power supply to be in the range 3 to 6V. A 74LS output cannot reliably drive a or 74HC input unless a 'pull-up' resistor of 2.
Driving or 74HC inputs from a 74LS output using a pull-up resistor. The has Schmitt trigger inputs to provide good noise immunity. They are ideal for slowly changing or noisy signals. These are ripple counters so beware that glitches may occur in any logic gate systems connected to their outputs due to the slight delay before the later counter outputs respond to a clock pulse.
The count advances as the clock input becomes low on the falling-edge , this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain.
For normal use connect QA to clockB to link the two sections, and connect the external clock signal to clockA. For normal operation at least one reset0 input should be low, making both high resets the counter to zero , QA-QD low.
Note that the has a pair of reset9 inputs on pins 6 and 7, these reset the counter to nine so at least one of them must be low for counting to occur.
Counting to less than the maximum 9 or 15 can be achieved by connecting the appropriate output s to the two reset0 inputs. If only one reset input is required the two inputs can be connected together.
For example: to count 0 to 8 connect QA 1 and QD 8 to the reset inputs. For normal use connect QA to clockB and connect external clock signal to clockA. Please see below for details of connecting ripple counters like the and in a chain. The contains two separate decade 0 to 9 counters, one on each side of the IC. They are ripple counters so beware that glitches may occur in any logic gate systems connected to their outputs due to the slight delay before the later counter outputs respond to a clock pulse.
For normal operation the reset input should be low, making it high resets the counter to zero , QA-QD low. Counting to less than 9 can be achieved by connecting the appropriate output s to the reset input, using an AND gate if necessary.
Please see below for details of connecting ripple counters like the in a chain. The contains two separate 4-bit 0 to 15 counters, one on each side of the IC.
They are ripple counters so beware that glitches may occur in logic systems connected to their outputs due to the slight delay before the later outputs respond to a clock pulse.
This is the usual clock behaviour of ripple counters and it means means a counter output can directly drive the clock input of the next counter in a chain. Counting to less than 15 can be achieved by connecting the appropriate output s to the reset input, using an AND gate if necessary. The diagram below shows how to link ripple counters in a chain, notice how the highest output QD of each counter drives the clock input of the next counter. These are synchronous counters so their outputs change precisely together on each clock pulse.
This is helpful if you need to connect their outputs to logic gates because it avoids the glitches which occur with ripple counters. The count advances as the clock input becomes high on the rising-edge. The decade counters count from 0 to 9 to in binary.
The 4-bit counters count from 0 to 15 to in binary. When low it resets the count to zero , QA-QD low , this happens immediately with the and standard reset , but with the and synchronous reset the reset occurs on the rising-edge of the clock input. Counting to less than the maximum 15 or 9 can be achieved by connecting the appropriate output s through a NOT or NAND gate to the reset input.
For the and synchronous reset you must use the output s representing one less than the reset count you require, e. Please see below for details of connecting synchronous counters like the ICs in a chain.
The diagram below shows how to link synchronous counters such as , notice how all the clock CK inputs are linked. Carry out CO is used to feed the carry in CI of the next counter.
Carry in CI of the first counter should be high. These counters have separate clock inputs for counting up and down. The count increases as the up clock input becomes high on the rising-edge. The count decreases as the down clock input becomes high on the rising-edge. In both cases the other clock input should be high.
For normal operation counting the preset input should be high and the reset input low. When the reset input is high it resets the count to zero , QA-QD low.
Note that a clock pulse is not required to preset, unlike the counters. For pin connections and functions please see:.
The outputs are active-low which means they become low when selected but are high at other times. They can sink up to about 20mA. The appropriate output becomes low in response to the BCD binary coded decimal input. The is a BCD binary coded decimal decoder intended for input values 0 to 9 to in binary. With inputs from 10 to 15 to in binary all outputs are high. Also see: 74HC and both are a decade counter and 1-of decoder in a single IC.
A common anode display is required. Display test and blank input are active-low so they should be high for normal operation. When display test is low all the display segments should light showing number 8. If the blank input is low the display will be blank when the count input is zero This can be used to blank leading zeros when there are several display digits driven by a chain of counters.
The is intended for BCD binary coded decimal which is input values 0 to 9 to in binary. Inputs from 10 to 15 to in binary will light odd display segments but will do no harm. For pin connections and functions please see Inputs have very high impedance resistance , this is good because it means they will not affect the part of the circuit where they are connected.
However, it also means that unconnected inputs can easily pick up electrical noise and rapidly change between high and low states in an unpredictable way.
This is likely to make the IC behave erratically and it will significantly increase the supply current. Note that 74HC inputs cannot be reliably driven by 74LS outputs because the voltage ranges used for logic 0 are not quite compatible. Outputs can sink and source about 4mA if you wish to maintain the correct output voltage to drive logic inputs, but if there is no need to drive any inputs the maximum current is about 20mA.
Gate propagation time : about 10ns for a signal to travel through a gate. Frequency : up to 25MHz. It is much greater at high frequencies, a few mW at 1MHz for example. In addition to the normal supply smoothing, a 0. Inputs 'float' high to logic 1 if unconnected, but do not rely on this in a permanent soldered circuit because the inputs may pick up electrical noise.
Frequency : up to about 35MHz under the right conditions. Power consumption of the IC itself is a few mW. Note that a series output can drive only one 74LS input. Connecting in a chain Please see below for details of connecting ripple counters like the and in a chain. Connecting in a chain Please see below for details of connecting ripple counters like the in a chain.
Note that the can be used as a 1-of-8 decoder if input D is held low.
74 Series Logic ICs
74161 COUNTER. Datasheet pdf. Equivalent
Synchronous 4 Bit Counters; Binary, Direct Reset